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CoreU1LL UTOPIA Level 1 Link-Layer Interface
cell, the CoreU1LL PHY-Layer device sends cells back-to-
back ( Figure 4 on page 3 ).
U1_tx_clk
U1_tx_clav
U1_tx_en
U1_tx_soc
If the user interface continues to assert w_avail during
the last two bytes of the current cell transfer, and one or
more complete ATM cells are ready to be transferred
(u1_rx_clav is high), the CoreU1LL accepts back-to-back
cells, as shown in Figure 7 .
U1_rx_clk
U1_rx_clav
U1_tx_data
P51 P52 P53 P54
H1
H2
H3
H4
H5
H6
U1_rx_en
Figure 4 ? Tx Back-to-Back Transfer
U1_rx_soc
U1_rx_data
P51 P52 P53 P54
H1
H2
H3
H4
H5
Rx Interface (Ingress)
The Rx interface operates in a similar manner to the Tx
interface. The PHY-Layer device indicates that it has a cell
ready to transfer by asserting u1_rx_clav high. Then, the
user interface is ready to accept a cell (w_avail high). The
CoreU1LL will initiate a transfer on the Rx interface by
asserting u1_rx_en low ( Figure 5 ).
u1_rx_clk
u1_rx_clav
u1_rx_en
u1_rx_soc
Figure 7 ? Rx Back-to-Back Transfer
User Interface
The user interface can connect directly to Actel's
CoreATMBUF3 cell buffer, an intellectual property core
that provides buffering for up to three, 54-byte ATM
cells in each direction ( Figure 1 on page 1 ). Alternatively,
the designer may connect his/her own cell buffer or user
logic function directly to the user interface. The signals
associated with the user interface are summarized in
Table 3 .
Table 3 ? User Interface Signals
u1_rx_data
H1 H2
Signal
reset
Type Description
In
Active high – resets all registers
Figure 5 ? Rx Start of Cell Transfer
The PHY-Layer device then asserts u1_rx_soc high,
indicating that the first word of the cell transfer is active
on the bus. Once a transfer has begun, all 53 or 54 bytes
of the cell are transferred without interruption.
If polling during the current transfer indicates that there
are no more cells available, or if the CoreU1LL is unable
to accept another cell from the PHY-Layer device, the
CoreU1LL deselects the physical interface by deasserting
u1_rx_en after receiving the last byte of the current cell,
as illustrated in Figure 6 .
u1_rx_clk
xlate
w_avail
w_phy_act
w_enable
w_adr
w_data
r_avail
r_buf_en
r_adr
r_data
In
In
Out
Out
Out
Out
In
Out
Out
In
53- / 54-byte cell size control
Active high – user ready to receive
Active high physical selected
Active high data enable
5-bit word count
16-bit data bus
Active high – user ready to send
Active high read enable
5-bit word count
16-bit data bus
u1_rx_clav
u1_rx_en
u1_rx_soc
When reset is asserted high, all registers in the CoreU1LL
are cleared. They will remain in this state as long as reset
is asserted.
If the xlate input is low, the CoreU1LL transfers data to/
u1_rx_data
P51 P52 P53 P54
XX
from the PHY-Layer device as 53-byte ATM cells. On
ingress (Rx), the CoreU1LL will duplicate the fifth byte of
Figure 6 ? Rx End of Transfer
v4.0
the ATM header and insert it as the sixth byte (UDF2) in
order to create a standard 54-byte ATM cell on the user
3
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相关代理商/技术参数
COREU1LL-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1LL-XX 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1LL UTOPIA Level 1 Link-Layer Interface
COREU1PHY-AN 制造商:Microsemi Corporation 功能描述:COREU1PHY-UTOPIA LEVEL 1 PHY INTERFACE - Virtual or Non-Physical Inventory (Software & Literature)
COREU1PHY-AR 功能描述:IP MODULE COREU1PHY RoHS:否 类别:编程器，开发系统 >> 软件 系列:* 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
COREU1PHY-EV 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CoreU1PHY - UTOPIA Level 1 PHY Interface